A roundup of commercially-available payload processors from around the world, for CubeSats and other satellite form factors.
Payload processor sytems manage the data collected by a satellite payload so that they can be stored, interpreted, and used by the on-board computer (OBC) and communications system. This enables the data to be processed by, or transferred to, other sub-systems when required in order for the satellite system to achieve its primary purpose.
This article gives a brief overview of payload data handling systems and shares details of commercially-available processor products from around the world. If you are familiar with the technology and would like to skip straight to the product listings, please click here.
What is a payload system?
Before explaining how payload processors work, we must first understand what is meant by a payload and a payload system.
The payload is the part of the satellite that gives it its primary function or purpose. The other sub-systems onboard support the satellite’s operational health, positioning, data transfer, power, and other processes that keep it running. But the payload provides the reason to keep that satellite running in the first place.
For Earth Observation (EO) applications, for example, the payload is the camera that is collecting the relevant data. For remote sensing satellites the payload will be the radar or other sensing equipment used to take readings.
Payload satellite communication is the transfer of data relating to the payload’s operation between the satellite and the ground.
To enable this, alongside the primary payload, the full set of antennas, receivers, and transmitters, both in-space and on the ground, used to transmit and store the data needed to meet mission objectives are sometimes referred to as the payload system.
As mentioned, the rest of the satellite (the bus, including the physical structure, electrical power system (EPS), attitude control components etc.) supports the payload and payload system.
What is a payload processor?
Payloads are an important area of innovation in the NewSpace sector. Electronic miniaturization and advances in the manufacture of other supporting sub-systems have brought new capabilities to payload developers.
In addition, innovation from outside of the space sector (such as in radar sensing and camera technology) has also made new missions and services possible.
Therefore satellites can now be launched, deployed, transported, and pointed with greater flexibility and accuracy than ever before. Once in position it is also possible to operate them in new, more powerful, and more responsive ways.
One of the net results of these changes has been greater demands on satellites in terms of data handling and exchange.
Modern EO cameras, for example, can capture more images, at a higher resolution, and in a greater number of formats every year. This requires more processing power in order to handle the data rates and volumes produced.
In addition, the available downlink bandwidth to ground stations can be limited, so satellite payload operators require solutions for coordinating higher volumes of data more efficiently.
The term on-board processing is often used to refer to the activities of the OBC – operational control of virtually all aspects of the satellite requiring computational control or data processing. Payload data processing instead refers specifically to the management of data from an individual payload.
And it is the payload processor that manages this data, and provides a vital connection between the payload, the satellite bus, and the on-board CPU / flight computer system.
Payload processors on the global market
In the section below you can find a variety of commercially-available payload processors on the global market.
We have also published an overview of FPGA-based payload processors and OBCs featuring some of these systems, as well as an in-depth article on how to choose an OBC for a satellite (in collaboration with STM, a participant in the satsearch membership program.)
These listings will be amended when new products are added to the global marketplace, or existing systems are upgraded, so please check back for more, or sign up for our mailing list for all the updates.
Click on any of the links below to find out more about the payload processors. You can also submit a request for a quote, documentation or further information on each of the products listed, or send us a more general query to discuss your specific needs, and we will use our global networks of suppliers to find a system to meet your specifications.
Radiation-tolerant EDGE payload processors provide on-board processing power ranging from 300 GFLOPS to >1 TFLOPS. Available in 1U and 3U form factors, and featuring 4 ARM cores with up to 2 GHz clock speed and 256 GPU cores with up to xyz clock speed.
The BST CDH system consist of 2 main parts: the OBC-100 and the ACC-100. The OBC-100 is responsible for scheduling all tasks and coordinating TMTC functions of the bus, whereas the ACC-100, which is integrated in the same housing, runs the attitude algorithm and connects to all ADCS components.
The Unibap iX5100 is a SpaceCloud® computer solution featuring an embedded, x86-compatible, and AMD® G-series SOC product from the 1st, 2nd, & LX families. The SOC is paired with a powerful Microsemi® SmartFusion2™ FPGA, which provides IO extension and board supervisory management.
The Alén Space TRISKEL - CubeSat OBC + TTC + OBSW Solution is an on-board computer, telemetry, tracking, and command hardware, and on-board software system for CubeSats. TRISKEL is a plug-and-play system featuring 'always-on' operation and 'no-code' development.
A 32g (with RJ45 connector) system, with typical power of 1W, based on a hybrid environment of CPUs and reprogrammable logic. The Q7 is a flight-proven processor board based on the Xilinx Zynq-7020, including ARM dual-core Cortex-A9 MPCore processors supported by programmable logic resources.
A 24g (without RJ45 connector) system, with typical power of 1W. The Q7S consists of a Q7 card equipped with space-ready software and firmware based on a hybrid environment of CPUs and reprogrammable logic. The library of logic and software functions is augmented by onboard analog and digital I/O.
A 64g (with power barrel & RJ45) system based on a hybrid environment of multi-core CPUs and reprogrammable logic. The Q8 includes a Xilinx Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC) Processing FPGA & memory resources such as LPDDR4 RAM (with EDAC), 2x QSPI Flash (NOR), and 2x eMMC.
A 56g (without power barrel & RJ45) system with > 25 krad radiation tolerance. The Q8S consists of a Q8 card equipped with space-ready software and firmware based on a hybrid environment of CPUs and reprogrammable logic. The library of logic and software functions is augmented by onboard digital I/O.
The Q8J extends the capability of the Xiphos Q8 processor, adding support for high speed JESD204B interfaces and access to external DDR3 or DDR4 memory. Suitable for SDR applications, the Q8J is delivered with a detachable PIM with standard interfaces, debug LEDs & other lab development features.
The Q8JS extends the capability of the Xiphos Q8 card with support for high speed JESD204B interfaces and access to external DDR3 or DDR4 memory. Suitable for SDR applications, the Q8JS consists of a Q8J card equipped with space-ready software and firmware plus a library of logic functions.
The Micro Satellite Processor Unit (MICROSATPRO) is an OBC compatible with microsatellite platforms. It is a control unit that has high fault tolerance and processing power specifications for difficult space conditions.
The Nano-Satellite Processor Unit (NANOSATPRO) is an OBC compatible with nanosatellite platforms for advanced space missions. It has an operating system running on an FPGA (soft processor-based) and supports the most common interfaces (UART, RS485, CAN, SPI, I2C, etc.).
A CubeSat standard-compliant Data Processing Unit (DPU) designed for the application of AI solutions in space. Leopard uses Deep Neural Networks to process data on-board and features FPGA to implement deep learning algorithms. The system has a throughput of up to 3 Tera Operations per second.
The OBC combines a Telemetry, Tracking & Command (TT&C) module & a Data Processing Unit (DPU). The TT&C unit features a TMS570 Hercules microcontroller, including a dual 300 MHz ARM Cortex-R5F with FPU in lock-step. The DPU is equipped with a Zynq UltraScale+ MPSoC including FPGA for customization.
The KP Labs' Lion is a data processing unit for advanced operations with the use of artificial intelligence and on-board data processing. The Lion DPU is dedicated to micro and small satellites weighing between 50 and 500kg.
A reconfigurable processing platform for nanosatellites that can be used as an OBC or as a payload processor. The FPGA-based architecture enables reconfiguring of communication interfaces and GPIOs based on system requirements, and avoids hardware obsolescence due to changing engineering demands.
A reconfigurable processing platform for nanosatellites that can be used as an OBC or as a payload processor. The system features a integrated Cortex M3 processor that can be programmed similar to a conventional microprocessor and custom FPGA configuration is available.
A 130g OBC with 10 kRAD radiation tolerance and RTEMS real-time operating system that runs on a 50 MHz LEON3FT fault-tolerant soft processor, compliant to IEEE 1754 SPARC v8. The system has a power rating of 1.3 W & fault tolerance secured via triple-modular redundancy on FPGA and memory scrubbing.
A processing platform with a Linux-based operating system that allows users to run various algorithms as distinct, uploadable applications. Using the optional, radiation-tolerant, storage module users can store up to 7.5 Gb of data, and can optionally store over 64 GB of bulk data on 2 SD cards.
Innoflight’s Trillion FLoating-point Operations Per second (TFLOP) computer is designed for LEO operations and includes an ARM Cortex-A15 (up to 2.32 GHz) processor and a Xilinx Ultrascale+ FPGA system. It also features a scalable number of GPU hardware accelerators.
CHAMPS is provided with CubeSat-compatible SWaP, with an 82 mm x 82 mm enclosure and dynamically configurable performance with power ranging from ~0.6 W up to ~12 W. The system features a Xilinx MPSoC device with an ARM Cortex-A53 quad-core APU at up to 1 GHz.
Developed with the support of the Canadian Space Agency, the Magellan FPGA-RPP is designed for highly elliptical and geostationary orbits, Lagrange points, and deep space interplanetary missions. Its architecture allows for the correction of radiation-induced single event upsets (SEU).
A structured framework designed to facilitate data processing, automatic data selection, and autonomous tasking in space. The system is composed of independent hardware and software modules along with a specifically designed IDE (Integrated Development Environment), including a user GUI (Graphical User Interface).
Designed to offer a flexible, programmable and modular system that can operate as a single-board compact computer, suitable for a range of mission scenarios. The IPPM board has been designed for missions where several payloads share a common DPU (Data Processing Unit) and has a number of communications ports, combined with a LEON2 processor.
The Payload Data Handling Unit (PDHU) covers the complete processing chain of the data, from the payload instrument to the transmitter, and is well suitable for use in systems high data rates (up to several Gbps). The PDHU features high-density and high storage memory devices, in both SDRAM and Flash formats, and the system is suitable for storage and retrieval of payload data obtained by high-resolution instruments (e.g. SAR, Hyperspectral Cameras, etc.).
A payload processor/recorder system that can process satellite payload data streams at a rate of up to 10 Gbps. It includes the capability to receive, process, store, playback, and transfer data, in image or alternative formats.
A processing system, designed for both space payload and communication processing applications, that utilizes both commercial and radiation hardened components. The system has a PowerPC® e500 core and uses the VxWorks RTOS operating system, with the Linux RTOS also available as an option. It processes at 2450 DMIPS @ 1.066 GHz, and has 1 GB DDR2 of SDRAM memory and 1 GB of flash (upgrade to 4 GB optional).
Seakr's 2nd generation Command & Data Handling system has a warm space redundancy configuration. It collects data from several spacecraft sensors and controls numerous attitude effectors, ustilizing a fully-compliant CCSDS Processor and Command Operation Procedures (COP).
The 3rd Command & Data Handling system is a three slot 6U Box with a Power Supply Board (PSB), Input/Output Board (IOB), and a LEON Processor Card (LPC). It can process at 25 MIPS and has a power consumption of 14 W.
The Medusa Single Board Computer (SBC) is SEAKR’s fourth iteration of the PowerQUICC®-III high performance PowerPC Single Board Computer (SBC) product line. It features a PowerPC® e500 core delivering 2450 DMIPS @ 1.066 GHz, and is suitable for a variety of mission applications.
The Wolverine processor is a reconfigurable GEO Sat RF processor that uses 20nm UltraScale Field Programmable Gate Arrays (FPGAs) and Analog-to-Digital/Digital-to-Analog (ADC/DAC) devices. It features 3 Xilinx™ UltraScale FPGA processors/modules, 4 RF inputs/outputs per module, and is scalable to 6 RFP modules.
The fifth generation of SEAKR's ReConfigurable Computer (RCC®). Designed for space payload processing applications, it features 3x Virtex-5 FX-130T FPGAs, high speed SERDES I/O, and power consumption that is a function of the FPGA code utilization.
A derivative of SEAKR's 5th generation ReConfigurable Computer (RCC®). Designed for space payload processing applications, it has an extended 6U cPCI module with PCI, GPIO, and SERDES interconnects. It also features 3x Virtex-5 FX-130T FPGAs, 3 GB DDR-II SDRAM, and is conduction-cooled.
The Application Independent Processor (AIP™) is a flexible, modular processing platform that can be adapted to a variety of mission applications. It features an extended 6U CompactPCI and an RCC® FPGA Processor with Personality Mezzanine. The system has a 22 – 36 Vdc power supply (which is MIL-STD-461C compliant) and a spare 6U PCI slot.
The Hopping Dehopping Processor (HDP) is single-point failure immune, and contains two power supply modules (PSM), each with a ~400 W per supply. It is suitable for beamforiming, specialized communications, RF signal processing, and other applications.
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