Modern satellites employ a variety of computing systems to ensure that both individual sub-systems and overall operations are coordinated effectively, and that the data produced are processed efficiently. Space grade FPGA systems can play an important role in these processes.
In this article we take a look at processing systems based on field programmable gate array (FPGA) technology.
We first provide a brief introduction to the technology before giving an overview of commercially available products from suppliers around the world, for both FPGA-based on-board computers (OBCs) and payload processors.
What is FPGA and why is it used in space?
A field programmable gate array (FPGA) is essentially a semiconductor integrated circuit (IC) comprised of an array of logic blocks that can be configured (or programmed) during use by the end-user (i.e. in the field).
The difference between an FPGA and a microcontroller or microprocessor is in the programming approach.
While using a processor, the user functionality is to be adapted to the available instruction set of the processor. Moreover, simultaneous processing of multiple tasks requires multiple CPU cores or multiple threads inside the processor.
Therefore, programming a processor or microcontroller built around a processor needs a software-based approach, operating under the constraints of the instruction set and the processor architecture, and has inherent processing delays.
On the other hand, programming an FPGA is more hardware-based as an FPGA is essentially an IC with input/output ports and configurable digital circuitry.
The basic architecture of an FPGA is depicted in the image below.
An FPGA comprises of programmable logic blocks (also known as configurable logic blocks, or CLBs), programmable interconnects, and programmable input/output (IO) blocks.
Each logic block is comprised of look-up tables, multiplexers, and storage elements, and can perform data storage and arithmetic operations. The input/output blocks provide off-chip connections.
The programmable interconnect matrix forms the connections between the logic blocks and the input/output blocks, so as to realize the user-defined functionality.
The user program on the FPGA is basically a stream of 1s and 0s which is loaded into the memory cells. This decides the functionality of the individual CLBs (i.e. whether to perform data storage or an arithmetic operation) and the interconnects between the CLBs, resulting in a custom optimal digital design for the particular functionality.
There are several well-known manufacturers of FPGA chips such as Xilinx, Actel (now Microsemi), Altera, and Atmel.
Though the basic architecture of FPGA is similar across all these chips, there are still a number of differences between them. The most important distinction is the FPGA architecture implementation technology.
There are four main categories of FPGA technology:
The first category is SRAM-based FPGA technology in which the configuration data of the logic cells is stored in static memory SRAM (Static Random-Access Memory). SRAM-based FPGAs need to be configured (programmed) every time following power-on, as the SRAM memory that stores its configuration is volatile.
Upon power-on, the SRAM-based FPGA is either configured from the data stored on an off-chip external flash chip or configured through an external device such as a processor, through a JTAG interface. SRAM-based FPGAs are the most commonly used form of the technology and popular examples include Virtex and Spartan families from Xilinx.
SRAM-based FPGAs with internal flash
The second category is SRAM-based FPGAs that contain internal flash memory blocks, so that the configuration data can be stored on the FPGA chip itself, without having to be stored on an external off-chip flash memory. The Spartan-3AN family FPGA of Xilinx is one example of this category.
The third category consists of true flash-based FPGAs. In these systems the memory cells on the FPGA are flash memory and the configuration data is stored in these non-volatile flash memory cells. Microsemi’s ProASIC3 is one example of a flash-based FPGA.
The fourth category is antifuse-based FPGAs which are programmed by creating permanent conductive paths between logic blocks and input/output ports of the FPGA. However, they can only be programmed once, unlike the other three kinds.
The advantages the systems in this category offer are that they are absolutely non-volatile, with the smallest routing delays, and robust against radiation effects. This makes them an ideal choice for space grade FPGA applications that require low power and zero configuration time, but have no requirement for reconfiguration.
The Axcelerator family of FPGAs from Microsemi are one popular example of antifuse FPGAs.
Space grade FPGAs for in-orbit applications
For space applications, flash-based FPGAs have several advantages. The biggest benefit is that flash memory is inherently not affected by alpha or neutron radiation, making the flash-based FPGA drastically less prone to failures induced by single event upsets (SEU).
Another advantage is their low power. Each SRAM memory cell in an SRAM-based FPGA comprises of six transistors (more in the case of radiation-hardened FPGAs; the Xilinx Virtex-5QV family has 12 transistor SRAM cells for example) whereas in flash-based FPGAs the configuration cells use a single transistor.
This results in much lower leakage current per cell, which translates into exponentially lower leakage current across the entire space grade FPGA chip, and results in a flash-based FPGA consuming much lesser power compared to an SRAM-based FPGA.
Traditionally, flash memories had a larger hardware footprint than SRAM memories, which resulted in SRAM-based FPGAs being much denser than flash-based FPGAs and thereby higher performance.
But flash memory cells have become smaller, resulting in flash- based FPGAs matching SRAM-based FPGAs in performance, while maintaining their edge in the consumption of less power.
In addition, the hardware footprint of flash-based FPGAs is also smaller, as the overall hardware footprint of individual flash memory cells has become comparable to SRAM memory cells.
Another advantage of flash-based FPGAs in space applications is their ability to be configured almost instantly, as the configuration data is present on the FPGA itself. This is not the case with their SRAM counterparts, which take several milliseconds to configure from the memory present off-chip.
FPGA-based System-on-Chip (SoC) in space instrumentation
FPGA-based SoCs enable the designers of a computing platform to develop the system in both hardware and firmware.
FPGA-based SoC designs have several advantages over microcontroller or digital signal processor (DSP) based designs for space exploration missions.
Given their unique mission goals, and thereby computational needs, computing platforms for deep space missions have different requirements in terms of speed, peak power consumption per operation, floating point arithmetic, and peripherals for internal communication.
FPGA-based designs provide the flexibility to tailor all these features, peripherals, and controllers that may not be possible using a microcontroller or DSP-based design.
Re-programmability and IP reuse are further reasons to favor FPGAs over ASICs, though ASIC-based SoC designs offer better performance in terms of chip delays, power consumption, and speed.
Current generation FPGAs, with high logic density and increased performance, now allow the development of complex systems consisting of processing elements, peripheral interfaces, on-chip bus structures, and analog sensors, to be embedded onto a single System-on-Chip.
The Xilinx Virtex-5QV and Microsemi RTG4 are some of the popular space grade FPGAs on the market. The NX RH FPGA is another space grade FPGA introduced by the French company NanoXplore.
Space grade FPGA based OBCs and payload processors on the global marketplace
In this section you can find a range of FPGA-based systems that can act as on-board computers (OBCs), payload processors, or perform both functions as needed.
These listings will be amended when new products are added to the global marketplace, or existing systems are upgraded, so please check back for more, or sign up for our mailing list for all the updates.
We have also published an overview of OBCs available on the global market as well as an article on how to choose the right OBC for your mission.
Click on any of the links below to find out more about the space grade FPGA satellite systems. You can also submit a request for a quote, documentation or further information on each of the products listed, or send us a more general query to discuss your specific needs, and we will use our global networks of suppliers to find a system to meet your specifications.
Radiation-tolerant EDGE payload processors provide on-board processing power ranging from 300 GFLOPS to >1 TFLOPS. Available in 1U and 3U form factors, and featuring 4 ARM cores with up to 2 GHz clock speed and 256 GPU cores with up to xyz clock speed.
The EXA ICEPS is an all-in-one, configurable spacecraft system core, designed to be the central operational heart for CubeSats. ICEPS compresses the functions of many cards into a single, 25mm-thick system, using modularity for fully customizable hardware that can range from being simply an EPS or including a range of features.
The Micro Satellite Processor Unit (MICROSATPRO) is an OBC compatible with microsatellite platforms. It is a control unit that has high fault tolerance and processing power specifications for difficult space conditions.
The Nano-Satellite Processor Unit (NANOSATPRO) is an OBC compatible with nanosatellite platforms for advanced space missions. It has an operating system running on an FPGA (soft processor-based) and supports the most common interfaces (UART, RS485, CAN, SPI, I2C, etc.).
The Unibap iX5100 is a SpaceCloud® computer solution featuring an embedded, x86-compatible, and AMD® G-series SOC product from the 1st, 2nd, & LX families. The SOC is paired with a powerful Microsemi® SmartFusion2™ FPGA, which provides IO extension and board supervisory management.
A 32g (with RJ45 connector) system, with typical power of 1W, based on a hybrid environment of CPUs and reprogrammable logic. The Q7 is a flight-proven processor board based on the Xilinx Zynq-7020, including ARM dual-core Cortex-A9 MPCore processors supported by programmable logic resources.
A 24g (without RJ45 connector) system, with typical power of 1W. The Q7S consists of a Q7 card equipped with space-ready software and firmware based on a hybrid environment of CPUs and reprogrammable logic. The library of logic and software functions is augmented by onboard analog and digital I/O.
Daughterboard for Xiphos’ Q7 hybrid processor card, enabling the Q7 to be inserted into existing systems with high-bandwidth video or imagery streams. Featuring 2x Camera Link (2x Base, or 1x Medium, or 1x Full) interfaces, 4x SpaceWire interfaces, and 4x USB 2.0 Master ports, serial and GPIOs.
A 64g (with power barrel & RJ45) system based on a hybrid environment of multi-core CPUs and reprogrammable logic. The Q8 includes a Xilinx Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC) Processing FPGA & memory resources such as LPDDR4 RAM (with EDAC), 2x QSPI Flash (NOR), and 2x eMMC.
A 56g (without power barrel & RJ45) system with > 25 krad radiation tolerance. The Q8S consists of a Q8 card equipped with space-ready software and firmware based on a hybrid environment of CPUs and reprogrammable logic. The library of logic and software functions is augmented by onboard digital I/O.
The Q8J extends the capability of the Xiphos Q8 processor, adding support for high speed JESD204B interfaces and access to external DDR3 or DDR4 memory. Suitable for SDR applications, the Q8J is delivered with a detachable PIM with standard interfaces, debug LEDs & other lab development features.
The Q8JS extends the capability of the Xiphos Q8 card with support for high speed JESD204B interfaces and access to external DDR3 or DDR4 memory. Suitable for SDR applications, the Q8JS consists of a Q8J card equipped with space-ready software and firmware plus a library of logic functions.
The Q8 SDR (Software-Defined Radio) Dock is a daughterboard for Xiphos’ Q8 hybrid processor card enabling integration of a GOMspace NanoCom TR-600 SDR module, based on Analog Devices’ AD9361 wideband transceiver RF System on a Chip (RFSoC). Featuring PPS, CANBUS, serial, UART, & USB interfaces.
A 130g OBC with 10 kRAD radiation tolerance and RTEMS real-time operating system that runs on a 50 MHz LEON3FT fault-tolerant soft processor, compliant to IEEE 1754 SPARC v8. The system has a power rating of 1.3 W & fault tolerance secured via triple-modular redundancy on FPGA and memory scrubbing.
Designed for satellite constellations in LEO and deep space exploration missions, the 130g Sirius OBC LEON3FT is based on a 50 MHz LEON3FT fault-tolerant soft processor with the RTEMS real-time operating system (RTOS), compliant to IEEE 1754 SPARCv8. The system features 1.3 W power consumption.
The RAD5545™ SpaceVPX single-board computer (SBC) integrates a version 1.2 RAD5545 system-on-chip (SoC) processor, with volatile & non-volatile memory, on a 6U-220 format module, compliant to the ANSI/VITA 78.00 SpaceVPX standard. Can operate as payload or system controller in a SpaceVPX backplane.
Featuring a Cortex-A53 Dual core @ 1.3 Ghz with ARM TrustZone and a Cortex-R5 Dual core @ 0.5GHz, the system can be used as either the main OBC or as a security add-on, for hosting confidential data and performing sensitive applications such as cryptographic operations.
A LEON-3FT (Dual Core) processor with interfaces to connect the AOCS, payload sub-system, and power sub-system, including SpaceWire and CAN. Featuring FPGA capability for customization, along with full-redundant architecture with 2 CPU boards, 2 IO boards and 2 power boards in Europe-Card format.
An OBC with a general-purpose hardware platform, suited for a range of satellite and CubeSat missions. It features a MSP430 (EP series) microcontroller and a Spartan-3E FPGA, organized in independent but cooperative cores, designed to provide hardware redundancy and common mode fault tolerance.
A reconfigurable processing platform for nanosatellites that can be used as an OBC or as a payload processor. The system features a integrated Cortex M3 processor that can be programmed similar to a conventional microprocessor and custom FPGA configuration is available.
A reconfigurable processing platform for nanosatellites that can be used as an OBC or as a payload processor. The FPGA-based architecture enables reconfiguring of communication interfaces and GPIOs based on system requirements, and avoids hardware obsolescence due to changing engineering demands.
Designed to offer a versatile, general-purpose processor solution for smallsats and nanosatellites. The system features a Xilinx Zynq System-on-Chip (SoC) device with an integrated ARM Cortex-A9 dual-core processor and can be provided with FPGA fabric for customer use.
CHAMPS is provided with CubeSat-compatible SWaP, with an 82 mm x 82 mm enclosure and dynamically configurable performance with power ranging from ~0.6 W up to ~12 W. The system features a Xilinx MPSoC device with an ARM Cortex-A53 quad-core APU at up to 1 GHz.
Innoflight’s Trillion FLoating-point Operations Per second (TFLOP) computer is designed for LEO operations and includes an ARM Cortex-A15 (up to 2.32 GHz) processor and a Xilinx Ultrascale+ FPGA system. It also features a scalable number of GPU hardware accelerators.
The OBC combines a Telemetry, Tracking & Command (TT&C) module & a Data Processing Unit (DPU). The TT&C unit features a TMS570 Hercules microcontroller, including a dual 300 MHz ARM Cortex-R5F with FPU in lock-step. The DPU is equipped with a Zynq UltraScale+ MPSoC including FPGA for customization.
A CubeSat standard-compliant Data Processing Unit (DPU) designed for the application of AI solutions in space. Leopard uses Deep Neural Networks to process data on-board and features FPGA to implement deep learning algorithms. The system has a throughput of up to 3 Tera Operations per second.
Developed with the support of the Canadian Space Agency, the Magellan FPGA-RPP is designed for highly elliptical and geostationary orbits, Lagrange points, and deep space interplanetary missions. Its architecture allows for the correction of radiation-induced single event upsets (SEU).
A 60g (without heat sink) compute platform for single- and double-precision operations, compatible with nanosatellites. Featuring < 1 TFLOPs processor performance, the system is based on Xilinx Ultrascale+ MPSoCs with dual-core ARM cortex A53 and R5 64-bit processing cores, and LPDDR4 memory.
A 60g (without heat sink) compute platform for single- and double-precision operations, compatible with nanosatellites. Featuring 1 to 5 TFLOPS processor performance, the system is based on Xilinx Ultrascale+ MPSoCs with dual-core ARM cortex A53 and R5 64-bit processing cores, and LPDDR4 memory.
An 80g (without heat sink) compute platform for single- and double-precision operations, compatible with nanosatellites. Featuring 3 to 15 TFLOPS processor performance, the system is based on Xilinx Ultrascale+ MPSoCs with dual-core ARM cortex A53 and R5 64-bit processing cores, and LPDDR4 memory.
The fifth generation of SEAKR's ReConfigurable Computer (RCC®). Designed for space payload processing applications, it features 3x Virtex-5 FX-130T FPGAs, high speed SERDES I/O, and power consumption that is a function of the FPGA code utilization.
A derivative of SEAKR's 5th generation ReConfigurable Computer (RCC®). Designed for space payload processing applications, it has an extended 6U cPCI module with PCI, GPIO, and SERDES interconnects. It also features 3x Virtex-5 FX-130T FPGAs, 3 GB DDR-II SDRAM, and is conduction-cooled.
Designed for the radiation environment of NASA’s Multiscale Magnetospheric Mission, the ZIN Technologies Single Board Computer (SBC) is based on a Leon3FT processor and is capable of 30 DMIPS and 4MFLOPS. Includes Actel RTAX FPGAs and can be customized with additional interfaces and memory.